Semiconductor components, such as ball grid array (BGA) and chip scale packaging (CSP) components, are one significant source of field failures in semiconductor devices, especially in portable and hand held devices such as cell phones. CSPs and BGAs will fail as a consequence of shock impact from mechanical shock and fatigue from thermal and bending cycling. CSPs and BGAs fail mainly due to failure in interconnection between a component and a printed wiring board (PWB) i.e. in an interconnection or PWB built up failure. Furthermore, high loading of interconnections may cause component internal failures, e.g. substrate or die cracking.
General examples of a prior art semiconductor components are illustrated in FIGS. 1a–1e. Specifically, FIGS. 1a–1e illustrate an integrated circuit component 20 that has interconnections 10 arranged in some two-dimensional layout in order to form an interconnection pattern. The interconnections 10 allow the component 20 to be electrically connected to other external devices, other peripherals, or other integrated circuits over conductive traces of a printed wiring board (PWB) or other substrate whereby larger electrical systems may be created (e.g. a computer, cell phone, television, etc.). In the prior art FIGS. 1a–1e, the interconnections 10 are aligned into rows and columns to form an interconnection pattern which has a rectangular shape with sharp corners. All interconnections 10 are of the same size but it is possible that some of the interconnections could have smaller or larger diameter.
One significant cause for failures is that loading is not distributed evenly between interconnections of the component. Typically corner interconnections meet the highest load and fail first.
Coefficient of thermal expansion (CTE) mismatch and temperature differences or fluctuations cause a component and a printed wiring board (PWB) to expand at different rate and magnitude. FIG. 2 illustrates in a simplified manner a cross sectional view of the ball grid array package 30 mounted on a printed wiring board 31 before deformation and FIG. 3 illustrates the same after deformation. It can be seen that the longer the distance from the component 32 center point is the higher deformation and stress an interconnection 33 have to undergo. Therefore, the corner solder joints 33′ have to deform the most and are thus typically the most critical ones.
As a consequence of shock impact from mechanical shock, a printed wiring board (PWB) is deformed. Deformation is dependent on supporting structures and loading. Due to an acceleration, PWB is bent up- or downward in the area between screws. A component mounted on the PWB tends to follow said deformation. This leads to uneven loading of the interconnections and the corner solder joints of the component are loaded the most. FIGS. 4 and 5 illustrate a simplified example of the PWB 40 during a shock impact. During the shock impact the PWB 40 is bent downwards forming kind of a flat bowl. A component 41 attached to the PWB 40 can be imagined as a piece of glass, which is put into the bowl as in FIG. 4. A weight 42 is put on the glass, which represents the phenomena that glass (component) should be able to follow the deformation of bowl (PWB). A first place of breakage is dependent on the bottom area of the weight while in a component it is dependent on die size (rigid area). In any case, the most likely locations for failure are the corners of the glass. Another potential failure locations would be the corners of the weight.
When the glass is round as illustrated in FIG. 5, the glass is supported from the whole edge area. There, stress is even, and the most critical locations would probably be the corners of the weight i.e. the solder joints close to the die edge. Thus, rounded ballout would distribute loading more evenly between the interconnections and thus reduce stresses in critical solder joints, and, furthermore, improve reliability.
Therefore, a need exists in the industry for a method of designing an interconnection pattern whereby overall product reliability is greatly improved while the compactness of CSP and BGA devices is not substantially and adversely affected.